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16th IEEE VLSI Test Symposium proceedings : April 26-30, 1998, Monterey, California by IEEE VLSI Test Symposium (16th 1998 Monterey, California)

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Published by IEEE Computer Society Press in Los Alamitos, California .
Written in English


  • Integrated circuits -- Very large scale integration -- Testing -- Congresses.

Book details:

Edition Notes

Other titlesVLSI Test Symposium
Statementsponsored by IEEE Computer Society Test Technology Technical Committee, IEEE Philadelphia Section.
ContributionsIEEE Computer Society. Test Technology Technical Committee., Institution of Electrical and Electronics Engineers. Philadelphia Section .
LC ClassificationsTK7874 .I26 1998
The Physical Object
Paginationxxxv, 472 p. :
Number of Pages472
ID Numbers
Open LibraryOL20880899M
ISBN 100818684364, 0818684380

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This work contains the proceedings from the 16th IEEE VLSI Test Symposium. Subjects covered include: core and processor test; RAM test; BIST; current testing techniques; delay test and diagnosis; fault modeling and parametric test; and analog . Vlsi Design (Vlsi Design ), 16th International Conference [IEEE Computer Society Symposium on VLSI] on *FREE* shipping on qualifying offers. The 87 papers in this proceedings of the January conference reflect the theme of convergence in system-on-a-chip design and the increasing need to design and verify hardware and software : IEEE Computer Society Symposium on VLSI. C Vishwanath Natarajan, Rajarajan Senguttuvan, Shreyas Sen and Abhijit Chatterjee, " ACT: Adaptive Calibration Test for Performance Enhancement and Increased Testability of Wireless RF Front-ends," in IEEE VLSI Test Symposium (VTS ). C The IEEE International Symposium on Computer Arithmetic (ARITH) is a conference in the area of computer arithmetic. The symposium was established in , initially as three-year event, then as a biennial event, and, finally, from as an annual ences: ACM/IEEE .

ªTowards variation-aware test methods,º in Proc. 16th IEEE European Test Symposium (ETS), , pp. ± [37] X. Qian and A. D. Singh, ªDistinguishing resistive small delay defects from random parameter variations,º in Proc. 19th IEEE . R. de Vries, A. J. E. M. Janssen, Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling, Proceedings of the 16th IEEE VLSI Cited by: Kao W, Chuang W, Lin H, Li J and Manquinho V () DFT and minimum leakage pattern generation for static power reduction during test and burn-in, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , (), Online publication date: 1-Mar Inaudible voice commands: The long-range attack and defense Roy, N., Shen, S., Hassanieh, H. & Choudhury, R. R., Jan 1 , Proceedings of the 15th USENIX Symposium on Networked Systems Design and Implementation, NSDI USENIX Association, p. 14 p. (Proceedings of the 15th USENIX Symposium on Networked Systems Design and .

VLSI Test Symposium (VTS'13), IEEE 31st, vol., no., pp, Berkly, CA April-May Conference paper AR: TBD Download Framework for dynamic estimation of . IEEE VLSI Test Symposium, Napa Valley, April 16th IEEE Latin-American Test Symposium (LATS), Mexico, March Conference Paper AR: TBD Download. Book Chapter AR: TBD% Download. A System for Collecting Activity Annotations for . Proc. IEEE 37th VLSI Test Symposium (VTS), Monterey, CA, April , algorithms are designed to produce test vectors using circuit’s timing information. He has served as program and organizing committee member of the 4th Biannual European - Latin American Summer School on Design, Test, and Reliability (BELAS). He served as organizing committee member of the 16th IEEE Latin American Test Symposium (LATS). His research interest is focused on the design and testing of VLSI digital circuits.